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Overview

Brain-inspired chip is a novel microchip that can simulate the information processed by human brain in real time. IBM built the world's first brain chip, developed two chip prototypes, and took another step forward on the road simulating human brain.

History

In 2008, after the successful development of a memristor, a key device that mimics brain function, DARPA launched a "Nerve Shape Adaptive Plastic Extensible Electronic System" (SyNAPSE) project with a total investment of US$101 million. Million neuron-level brain-inspired computing chips.

First generation brain-inspired chip

In August 2011, IBM first developed two prototypes of silicon chips with perceptual cognitive capabilities by simulating brain structures, which can have the ability to learn and process information like the brain, poccessing information more quickly and efficiently by strengthening or weakening the connection between neurons. IBM also successfully demonstrated the simple application of brain-like chips in the fields of navigation, pattern recognition, associative memory and classification, including the completion of maze games and bezel games, and pointed out that the "brain capacity" of such chips is only equivalent to the brain level.

Second generation brain-inspired chip

In August 2014, IBM introduced a second-generation brain chip called "TrueNorth" It is fabricated on a 28-nanometer silicon process, including 5.4 billion transistors and 4096 processing cores, equivalent to 1 million programmable neurons, and 256 million programmable synapses.

Compared with the first generation brain-like chips, the performance of the "TrueNorth" chip has been greatly improved. The number of neurons increased from 256 to 1 million, an increase of 3906 times; the number of programmable synapses increased from 262,144 to 256 million, an increase of 976 times; 46 billion synaptic operations per second, total power consumption only It is 70 milliwatts and consumes 20 milliwatts per square centimeter, which is 1/100 of the first generation brain chip; the "true north" processing nuclear volume is only 1/15 of the first generation brain chip.

Principle

A basic neuromorphic unit is composed of several synapses and a neuron block, as shown in Figure 5. It mimics biological neural cell whereby the synapses receive the synaptic spikes from the other connected neurons and convert them into currents according to their synaptic strength, and the neuron block performs spatiotemporal integration of the spiking pulses and generates output spikes similar to the operation of soma. Furthermore, the dendrites and axon blocks are implemented using interconnect circuits, which model the spiking signal propagation through the neuronal fibers.

Similar to a biological synapse, the conductance of resistive memory (or ReRAM) can be incrementally modified by controlling potential across it. Such resistance modulation shows the biological plausible STDP and SRDP rules. With nanoscale resistive synaptic devices and/or compact [[[CMOS]] resistive synaptic circuits, a versatile CMOS neuron that can interface with these resistive synapses becomes a critical piece to complete the puzzle of a large-scale brain-inspired neuromorphic chip.

Architecture

Non Von-Neumann architecture

With the emergence of the deep learning algorithm, the requirements for the computational power of the chip have been continuously improved, and the bottleneck of Von-Neumann is obvious: when the CPU needs to execute some simple instructions on a large amount of data, the data flow will seriously reduce the overall efficiency, and the CPU will be idle when the data is input or output.

Brain-inspired chip architecture is to simulate the synaptic transmission structure of human brain. Many processors are similar to neurons, and communication systems are similar to nerve fibers. The computation of each neuron is carried out locally. The overall task is divided, and each neuron is only responsible for part of the computation. This method has obvious advantages in processing large amounts of data, and the power consumption is lower than traditional chips. IBM's TrueNorth chip, for example, consumes only 20 milliwatts per square centimeter of power.

Standard CMOS Technology

Since the emergence of neuromorphic engineering, several silicon design styles have appeared. They model certain aspects of biological neuron, such as subthreshold biophysically realistic models, compact integrateand-fire neuron(IFN, a mathematical model of independent neurons) circuits, switched-capacitor neuron, and digital very large-scale integration (VLSI) implementations.

Figure 7 shows the circuit schematics of the leaky IFN neuron. It is composed of a single-ended opamp, an asynchronous comparator, a phase controller, a spike generator, three analog switches (SW1, SW2 and SW3), a capacitor Cmem for integration operation, and a leaky resistor Rleaky, which is implemented using a MOS transistor in triode. The neuron’s dual-mode operation and STDP-compatible spike generating are the key to overcome the challenges of existing IFN circuits, which can help it to fit into a real large-scale neuromorphic system with resistive synapses.

Block diagram of the event-driven leaky IFN circuit.

Deep Analysis and Optimization

Event-Driven Dual-Mode Operation

Event-driven dual-mode operation is realized by using a single opamp that is reconfigured as both an integrator and a driver for resistive load during firing events. Here, a power-optimized opamp operates in two asynchronous modes, i.e., integration and firing modes, as illustrated in Figure 8.

Dual-mode operation. (A) Integration mode: Opamp is configured as a leaky integrator to sum the currents injected into the neuron. Voltages of Vrefr are held for both pre- and post-resistive synapses. (B) Firing mode: Opamp is reconfigured as a voltage buffer to drive resistive synapses with STDP spikes in both forward and backward directions. Note that backward driving occurs at the same node (circled) of current summing, which enables in situ learning in bare synapses.

STDP-Compatible Spike Generation

The shape of the action potential function Vspk strongly influences the resulting STDP function in synapse. A bio-emulative STDP pulse with exponential rising edges is not suitable for circuit implementation. However, a similar STDP learning function in synapse can be achieved with a simpler action potential shape by implementing narrow short positive pulse of large amplitude and a longer relaxing slowly decreasing negative tail.

STDP-compatible spike generation with tunable parameters. These spikes are applied across resistive synapses and reduce their resistance if Vnet > Vt,p or increase their resistance if Vnet < −Vt,m.

Advantages and Disadvantages

Advantages

Existing formed circuits, such as TrueNorth created by IBM Lab ,basically, can only support the neurodynamic SNN algorithm. The support rate of the artificial neural network algorithm is pretty low, and the calculation power only rates 58 gops ,compared to the common speed of the general accelerator which ranks several tops .However TrueNorth has low power consumption .The 28nm process has an area of more than 430 millimeters, so his effective computing cost is only 10 points. Using a 2D Mesh chip network, the chip and chip can be directly connected through the LDVS serial port, so that good scalability becomes one of its biggest advantages.

Disadvantages

The combination of cost-saving, extremely low computing power, high power consumption ratio and high scalability is also a common phenomenon of many current morphological chips. They basically only support neurodynamic algorithms, which are more fluent and more mature. More powerful artificial neural network algorithms such as the CNN algorithm have low support, so these neuromorphic chips are now almost uncommercial and are still in the laboratory validation phase.

Application

On the issue of intelligent computing such as image recognition, voice recognition, machine translation, ad recommendation and data mining, brain-like chips can make a great difference.

Brain-inspired chips combined with traditional AI applications can increase the speed and accuracy of intelligent computing and reduce energy consumption. The artificial intelligence upgraded by brain-inspired chip will have the ability to understand the outside world through intelligent growth.

In some cases, devices such as VR and high-speed cameras require high real-time performance, so processing through the cloud might not be in time. At this time, brain-like chip can perform the inference step offline in the terminal devices.

The integration of brain-inspired chips and robots will give the robot the ability to visualize, hear, think and execute, and improve its cognitive, learning and motion control capabilities in a new environment. Brain-inspired robots will no longer be just human tools, but will work as human "colleagues" with people.

Future

Computer begin to "cognize" and " think"

In the future, if the research progresses smoothly, the brain-inspired chip will become the biggest change in the entire computer industry since the birth of the personal computer. Perhaps future computers will not only rely on computing speed and massive databases to work, they can also really "cognize" and "think", which will change the normal working mode of computers and explore more fields. Brain-inspired computing chips will meet the low energy requirements of mobile robots, remote sensors, drones, individual equipment, etc. Through continuous learning to achieve automatic information processing in complex environments, promote the development of highly autonomous intelligent robots.

Memristor Advancement

The neuron pathway has a plasticity dimension called STDP (Spike Timing Dependent Plasticity), which is the time Dependent relationship between the input and output pulses (Spikie) of the synaptic connection strength (Plasticity).The use of memristor which conduct the same effect as STDP(Spike Timing Dependent Plasticity) can bring brain-inspired computer into a new era. But High performance memristor compatible with advanced integrated circuits is still under development.

Exploration outside the realm of brain science

BrainScaleS research group plan to apply multi-scale information processing in the brain to computational tasks outside the realm of brain science. Test a new method for probabilistic inference in large Bayesian networks to networks of spiking neurons and implement this approach in the HMF. This approach could have important impacts in areas such as weather forecast, fluid dynamics, electromagnetism and many others. The possibility of using spiking neurons to solve PDEs, and more generally spiking neuron hardware as a tool to solve general classes of problems and equations, is a very promising direction for future ICT research.

See Also

• Biological machine
• Neuromorphic computing
• TrueNorth
• SpiNNaker
• SyNAPSE
• Human Brain Project
• Zeroth (software)
• Neurostimulation
• Neural circuit
• Neural coding
• Neural engineering
• Bio-inspired robotics
• Artificial inteligence